Historically, designers have focused on performance & cost but the proliferation of battery operated devices such as MP3 players, digital cameras, digital camcorders, and integrated wireless phones is turning design for low power into a mainstream design challenge.
Energy efficient systems must be energy efficient in both standby and active mode and especially the latter is very difficult to achieve with traditional low power hardware techniques and fabrication processes only. Energy efficient systems also require energy efficient software, algorithms and architectures.
In this seminar we will start with the core C algorithm of a common consumer device, and take it through a design flow that leads to a low power implementation of that C algorithm using tools from PowerEscape, ChipVision and CoWare.
Using the PowerEscape tools, participants will determine the optimal cache configuration & memory architecture for low power, highlight the energy bottlenecks in the C code and replace them with functionally equivalent C algorithms that accesses memory less frequently and therefore consumes less energy.
Using the ChipVision tools, participants will explore the energy efficiency of different hardware architectures of the top energy bottlenecks, and then do a similar analysis using the more energy efficient C algorithm.
Finally, CoWare will briefly demonstrate how these results flow in its hardware/software co-design environment.
Participants will leave the seminar with a good understanding of the benefits and main tasks involved in approaching design for low power from the system/algorithmic level.
Historically, designers have focused on performance & cost but the proliferation of battery operated devices such as MP3 players, digital cameras, digital camcorders, and integrated wireless phones is turning design for low power into a mainstream design challenge.